74HC Datasheet, 74HC stage Binary Counter Datasheet, buy 74HC, 74HC pdf, ic 74HC description/ordering information. The ‘HC devices are stage asynchronous binary counters, with the outputs of all stages available externally. A high. Data sheet acquired from Harris Semiconductor. SCHSD. Features. • Fully Static Operation. • Buffered Inputs. • Common Reset. • Negative.

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Did I miss something on the ripple counters? Surely the 74VHCwith its Mhz typical max clock frequency will do the job! About Us Contact Hackaday. I have to go take them out of my shopping cart now: The row address can be updated from the horizontal sync. I have a tube of 50 MHz cans around here that I could divide down, but since I have to order parts for this thing anyway, I might as well pick up the exact frequency for a few bucks.

I saw the 25 MHz trick in your terminal project – good to know. Those bounces won’t kill this project. How about the 74HC? Musta been a bunch of pixie-dust in there, or a poor memory of 18 years ago. I spent the afternoon re-working my ugly SOIC adapter board designs to reduce the ground-connection impedance and add on-board bypass caps. Cycling back the hsync for a second counter is interesting.

74HC Datasheet PDF –

This would work – with the 12ns SRAM access time, still way under the 40ns cycle time. I haven’t used VHC logic before, but keep seeing it around. 74hc040 clock input on the ‘ works on the positive edge, so the schematic above changes a bit, but at least the addresses seem OK. Sign up Already a member?


Here’s a simplified schematic of the guts of the VGA framebuffer it ignores the reset and connections between the two ”s required to generate 19 bits of address.

Interestingly, it also has a synchronous clear, and connections for synchronous expansion between counters with lookahead carry outputs. Now, I need 5 ICs to make the counter – if it’s even fast enough. So, what the heck, I’ll look at timing before slapping something together. The dot clock is Synchronous Counters Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.

I’m using typical values for the moment; if it doesn’t work there, it’s not going to work worst-case, either. In the store-each-dot-period-as-a-byte plan, this is trivial – I have full and easy control of all the singals on on a per-dot basis.


That should relax some timing as your MSB are no longer rely on the propagation from the lower bits. Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.


Since it’s a ripple counter, Q0 flips, then Datasueet, then Q2, etc, so we have to add all the delays so see how long it takes for the address to settle to the next datashee.

I’m going to ignore those timing calculations for the moment next log because there’s an even bigger problem here – it takes too long for the address to settle. I’ll have to give that one some thought. So, with two of them connected to generate 19 bits of address, the tpd from the clock edge to the MSB settling is: I think either one would definitely work, and it would make an interesting project, but I’ve somehow got it into my head that I need actual x Add in the 12 ns access time of the SRAM, and we’re definitely over budget.

I’m already bummed about the color thing In this case, it’s not memory but registers. Synchronization is an issue, but it’s worth thinking about – maybe if the PIC runs from the external This could be interesting.

VHC to the rescue? It’s a shame, because the ‘ packs bits into a single package. 74ch4040 started with the VHC part this time: